1. Technical Field
The present invention relates in general to interconnects (or busses) and, in particular to signal propagation on interconnects. Still more particularly, the present invention relates to a method and system for improving the overall propagation speed of signals on interconnects.
2. Description of the Related Art
Increasing the propagation speed of signals traveling on interconnects (or busses) of a chip while concurrently reducing the size of the chip presents a significant challenge in chip development. Chips utilized as microprocessors require a high wire packing density for transmitting data due to their large on-chip memory structures. Technological improvements, such as continued complementary metal oxide semiconductors (CMOS) scaling, also reduce dimensions and spacings of the interconnect wires on the chip. Smaller spacing, however, increases coupling capacitance and results in longer delays in interconnects.
The performance of current and future microprocessors and other integrated circuits (ICs) are limited by delays in signal propagation along on-chip interconnections. On long, wide busses that are designed to switch simultaneously, the capacitive coupling (noise) induced delay can be as high as 50% of total propagation delay for wires formed with high level metals of the IC. This percentage, which may become even higher with further scaling, represents a significant performance limitation for high performance processors.
In current chip designs, the interconnect RC delay is minimized by optimizing buffer placement and buffer sizing and utilizing wires routed on non-minimum pitches. The capacitive coupling is reduced by increasing wire spacing or employing shielding wires between signal wires. Additional methods of reducing the capacitive coupling are sometimes utilized. One of these methods involves switching wire positions to reduce the length of coupling wire pairs and subsequently reduce the coupling effects of a neighboring wire. Another method involves introducing different phases for signals on neighboring wires. Drawbacks of these approaches include reduced numbers of available signal wires and an eventual increase in wire congestion at the chip integration level. In addition, optimal buffer placement often can not be implemented due to constraints of the overall chip floor-plan. Moreover, because of the difficulties and inaccuracy in modeling of coupling noise, unexpected timing failures can occur and may only be detected at a relatively late design phase. Addressing these failures usually requires redesigning the whole chip interconnect topology, which forces new changes on chip integration and often negatively impacts the product delivery schedule.
The present invention recognizes that it would be desirable to have a method and system for improving interconnect speed for high performance ICs such as processor chips. A method and system which speeds up lagging signal propagation without redesigning the interconnect and chip integration would be a welcomed improvement. These and other benefits are provided by the described inventions
Disclosed is a system for reducing propagation delays caused by coupling capacitance of RC interconnects. The system comprises a first interconnect utilized for propagating signals, a second interconnect also utilized for propagating signals but which propagates signals at a faster rate than the first interconnect, and a charge dumping circuit with an input coupled to a point on the second interconnect and an output coupled to a corresponding point on the first interconnect. The charge dumping circuit comprises a plurality of transistors and dumps charge from the second interconnect to the first interconnect to increase switching times of the signals propagating on the first interconnect and improve overall propagation speed.
In the preferred embodiment, the system comprises two interconnects adjacent to the first interconnect that are both connected to inputs of separate charge dumping circuits. Both adjacent interconnects dump a charge to the first interconnect to increase propagation speed of signals on the first interconnect. The charge dumping circuit comprises a select-signal generation circuit and two pulse generation circuits. The dump time and magnitude of the charge is controlled by these circuits, respectively. The outputs of the pulse generation circuits opens a p-type and n-type transistor to dump charge to the first interconnect.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.